#ifndef _S3C2440_H
#define _S3C2440_H

#define _REG(X)         (*(volatile unsigned int *)(X))
#define _REG_BYTE(X)    (*(volatile unsigned char *)(X))

#define BWSCON      _REG(0x48000000)
#define BANKCON0    _REG(0x48000004)
#define BANKCON1    _REG(0x48000008)
#define BANKCON2    _REG(0x4800000C)
#define BANKCON3    _REG(0x48000010)
#define BANKCON4    _REG(0x48000014)
#define BANKCON5    _REG(0x48000018)
#define BANKCON6    _REG(0x4800001C)
#define BANKCON7    _REG(0x48000020)

#define REFRESH     _REG(0x48000024)
#define BANKSIZE    _REG(0x48000028)
#define MRSRB6      _REG(0x4800002C)
#define MRSRB7      _REG(0x48000030)

#define SRCPND      _REG(0X4A000000)
#define INTMOD      _REG(0X4A000004)
#define INTMSK      _REG(0x4A000008)
#define PRIORITY    _REG(0x4A00000C)
#define INTPND      _REG(0X4A000010)
#define INTOFFSET   _REG(0x4A000014)
#define SUBSRCPND   _REG(0X4A000018)
#define INTSUBMSK   _REG(0X4A00001C)

#define CLKDIVN     _REG(0x4C000014)
#define MPLLCON     _REG(0x4C000004)
#define UPLLCON     _REG(0x4C000008)

/* LCD CONTROLLER */
#define LCDCON1     _REG(0X4D000000)
#define LCDCON2     _REG(0X4D000004)
#define LCDCON3     _REG(0X4D000008)
#define LCDCON4     _REG(0X4D00000C)
#define LCDCON5     _REG(0X4D000010)
#define LCDSADDR1   _REG(0X4D000014)
#define LCDSADDR2   _REG(0X4D000018)

/* NAND FLASH*/
#define NFCONF      _REG(0x4E000000)
#define NFCONT      _REG(0x4E000004)
#define NFCCMD      _REG_BYTE(0x4E000008)
#define NFADDR      _REG_BYTE(0x4E00000C)
#define NFDATA      _REG_BYTE(0x4E000010)


#define NFSTAT      _REG_BYTE(0x4E000020)

#define ULCON0      _REG(0x50000000)
#define ULCON1      _REG(0x50004000)
#define ULCON2      _REG(0x50008000)
#define UCON0       _REG(0x50000004)
#define UCON1       _REG(0x50004004)
#define UCON2       _REG(0x50008004)
#define UFCON0      _REG(0x50000008)
#define UFCON1      _REG(0x50004008)
#define UFCON2      _REG(0x50008008)
#define UTRSTAT0    _REG(0x50000010)
#define UTRSTAT1    _REG(0x50004010)
#define UTRSTAT2    _REG(0x50008010)
#define UTXH0       _REG_BYTE(0x50000020)
#define UTXH1       _REG_BYTE(0x50004020)
#define UTXH2       _REG_BYTE(0x50008020)
#define URXH0       _REG_BYTE(0x50000024)
#define URXH1       _REG_BYTE(0x50004024)
#define URXH2       _REG_BYTE(0x50004027)
#define UBRDIV0     _REG(0x50000028)
#define UBRDIV1     _REG(0x50004028)
#define UBRDIV2     _REG(0x50008028)

#define TCFG0       _REG(0x51000000)
#define TCFG1       _REG(0x51000004)
#define TCON        _REG(0x51000008)
#define TCNTB0      _REG(0x5100000C)
#define TCMPB0      _REG(0x51000010)

#define GPBCON      _REG(0x56000010)
#define GPBDAT      _REG(0x56000014)

#define GPCCON      _REG(0x56000020)
#define GPCDAT      _REG(0x56000014)
#define GPCUP       _REG(0x56000028)
#define GPDCON      _REG(0x56000024)
#define GPDDAT      _REG(0x56000014)
#define GPDUP       _REG(0x56000038)

#define GPFCON      _REG(0x56000050)
#define GPFDAT      _REG(0x56000054)
#define GPFUP       _REG(0x56000058)

#define GPGCON      _REG(0x56000060)
#define GPGDAT      _REG(0x56000064)
#define GPGUP       _REG(0x56000068)

#define GPHCON      _REG(0x56000070)
#define GPHDAT      _REG(0x56000074)
#define GPHUP       _REG(0x56000078)

#define EXTINT0     _REG(0x56000088)
#define EXTINT1     _REG(0x5600008c)
#define EXTINT2     _REG(0x56000090)

#define EINTMASK    _REG(0x560000a4)
#define EINTPEND    _REG(0x560000a8)

#endif
